1. Field of the Invention
This invention is related to the field of integrated circuits, and more particularly, to designing and developing high-performance microprocessors.
2. Description of the Related Art
Typically, components of high-performance integrated circuits, such as microprocessors, are designed at the custom transistor level (e.g. using individual transistors, resistors and capacitors). Often state-of-the-art microprocessors are designed with feature sizes and operational speeds that have never before been achieved. Additionally, many of the required functions may be new/unique to this particular design. Traditionally, a circuit designer builds up the required function from discrete transistors tailoring each one to its exact requirements in order to produce a design that consumes minimal real estate and power, while delivering the needed performance. While excellent performance and area results may be obtained, such custom transistor-level design is very time consuming.
In order to validate his design, the designer may use one or more transistor level modeling tools, such as SPICE or HSPICE. These tools may provide extremely accurate simulation results, but may require relatively large amounts of computer resources and time to perform their functions. For example, a relatively simple design including a dozen or so transistors and associated components may require hours of simulation time for thorough analysis. Given that this simulation time may be exponentially proportional to the number of circuit elements, the validation time required for a custom transistor level design of even moderate complexity may quickly become daunting.
Generally, when the transistor level design/modeling of a function is complete, the designer generates transistor level model for verification. Typically, this verification may be done with respect to a Register Transfer Level (RTL) model that has itself been verified against the design specification. The verification of transistor level models is frequently an almost entirely manual operation, which may be extremely time consuming due to the unavailability of automated verification tools capable of operating on transistor level (TRL) models.